1. Field of the Invention
This invention relates to a semiconductor memory device such as a random access memory (RAM) and a read only memory (ROM).
2. Description of the Related Art
FIG. 1 is a block diagram showing the structure of a conventional memory device; for example, a one mega byte dynamic RAM (DRAM). The internal circuit operation of the DRAM is schematically represented by the timing charts of FIGS. 2 and 3.
In one cycle, a row address and a column address are retrieved by an internal circuit at a trailing edge of a RAS (Row Address Strobe) clock and at a trailing edge of a CAS (Column Address Strobe) clock, respectively. At the same time the column address is retrieved, it is determined whether the cycle is a writing cycle or a reading cycle, in accordance with the level "H" or "L" of the WRITE signal. Upon completion of a data-writing or data-reading, the RAS clock rises again, and the internal circuit is put into a stand-by state in which it is ready for a next operation.
The DRAM shown in FIG. 1 operates either in reading mode or writing mode under the control of three clock signals, RAS, CAS, and WRITE. In the reading mode, it performs row selection, detection of data within a cell, column selection, data-outputting, and stand-by. All of these operations, except for standby, are performed by the DRAM during each RAS-cycle period, i.e., from the trailing edge of the RAS clock to the next trailing edge thereof. Obviously, the RAS-cycle period determines the number of data items which can be read from the DRAM per unit time, which is generally known as "data rate". To increase the data rate, the RAS-cycle period must be shortened by raising the operation speed of the DRAM. However, it is difficult to sufficiently increase the operation speed of the DRAM with the technology now available. In other words, the DRAMs now available can operate only at speeds far lower than that of CPUs (Central Processing Units).
To achieve a high data rate in DRAMs, various methods have been devised. One of them is to drive the circuits incorporated in a DRAM in page mode, as is shown in FIG. 4. Another of these methods is to drive the circuits in static column mode as is illustrated in FIG. 5. Still another of these methods is to drive the circuits in nibble mode as will be explained with reference to FIGS. 6 and 7.
In the page mode, one of the memory-cell rows of the DRAM is selected for a predetermined period during which the RAS clock is at a low level V.sub.IL. Then, some of the memory-cell columns are selected by column select signals which are generated in response to successive CAS clock pulses. The column select signals are supplied to input/output gates from the column decoder, whereby data is read from those memory cells of the selected row which belong to the columns designated during the CAS clock pulses. In the page mode, once one memory-cell row is selected, it is no longer necessary to select the same row repeatedly in order to read data from the cells of this row. As a comparison of FIG. 4 with FIGS. 2 and 3 clearly indicates, the data rate achieved by driving the internal circuits in the page mode is higher than when the circuits are driven in the mode shown in FIGS. 2 and 3.
In the static column mode, one of the memory-cell rows of the DRAM is selected in accordance with the corresponding row address. While this row is in the selected state, some column select signals are supplied to the input/output gates from the column decoder, whereby data is read from those of the memory cells selected row which belong to the columns designated by the column select signal. In the static column mode, too, once one row is selected, it is no longer necessary to select the same row repeatedly in order to read data from the cells of this row. As a comparison of FIG. 5 with FIGS. 2 and 3 clearly indicates, the data rate achieved by driving the internal circuits in the static column mode is higher than when the circuits are driven in the mode shown in FIG. 2 or 3.
The nibble mode can be applied to a DRAM having the structure shown in FIG. 6. In the nibble mode, once one of the memory-cell rows and one of the memory-cell columns are selected in accordance with the corresponding row address and column address, 4-bit data are read consecutively, the first one of which is designated by the row and column addresses, without supplying the column address to select the cells, as is illustrated in FIG. 7. As may be understood from FIG. 7 in comparison with FIG. 5 with FIGS. 2 and 3, the data rate achieved by driving the internal circuits in the nibble mode is higher than when the circuits are driven in the mode shown in FIG. 2 or 3.
Further, a so-called dual port RAM is known, which has a serial register. Once one of the memory-cell rows and one of the memory-cell columns are selected in accordance with the corresponding row address and column address, data is consecutively read from a serial register, the first one of which is designated by the row and column addresses and the number of which is equal to or less than the digits of the serial register, without supplying the column address during each RAS-cycle period. Therefore, the data rate achieved in the dual port RAM is higher than when the circuits are driven in the mode shown in FIG. 2 or 3.
The first method of driving the internal circuits in the page mode, and the second method of driving the circuits in the static column mode, however, cannot achieve random access to the memory cell array; they achieve nothing other than pseudo-serial access. The third method of driving the circuits in the nibble mode is disadvantageous in that the memory cells selected are always consecutive 4 cells forming a group, not the cells which are selected at random; the freedom of choice is limited. The dual port RAM can indeed be accessed at high speed, but this high-speed accessing is serial, not random.